Semiconductor integrated circuit device

ABSTRACT

A semiconductor integrated circuit device has two semiconductor integrated circuit chips ( 20  and  30 ) respectively provided with a plurality of PADs ( 40   a - 40   e   , 41   a - 41   e  and  42   a - 42   d ), a plurality of LEADs ( 50   a - 50   d ) disposed around arrays of the semiconductor integrated circuit chips, and a plurality of bonding wires ( 60   a - 60   e  and  61   a - 61   d ). The plurality of bonding wires are connected so as not to straddle one semiconductor integrated circuit chip ( 30 ) and allow wiring between the PADs ( 40   a - 40   e ) of the other semiconductor integrated circuit chip ( 20 ) and the LEADs ( 50   a - 50   d ).

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor integratedcircuit device of an SIP (System In a Package) using semiconductorintegrated circuit chips with I/F (Interface) functions added thereto.

[0003] 2. Description of the Prior Art

[0004]FIG. 18 is a plan view showing a semiconductor integrated circuitdevice (related art example 1) of a conventional SIP (System In aPackage). In the drawing, reference numeral 10 indicates a bonding pad(bonding PAD), reference numeral 20 indicates a semiconductor integratedcircuit chip A (Chip A) disposed on the bonding PAD 10, and referencenumeral 35 indicates a semiconductor integrated circuit chip B (Chip B)excluding I/F functions, which is disposed on the bonding PAD 10,respectively. Reference numerals 40 a-40 e and 43 a-43 e respectivelyindicate pads (PADs) of the Chip A20, and reference numerals 41 a-41 eand 42 a-42 d respectively indicate pads (PADs) of the Chip B35.Reference numerals 50 a-50 f and 51 a-51 i respectively indicateconnecting leads (LEADs) disposed around the bonding PAD 10. Referencenumerals 60 b, 60 d and 60 e respectively indicate bonding wires forconnecting the Chip A20 and the Chip b35 or LEADs 50 a-50 f. Referencenumerals 62 a, 62 b, 62 d and 62 f respectively indicate bonding wiresfor connecting the Chip A20 and the LEADs 51 a-51 i. Reference numerals61 a-61 d respectively indicate bonding wires for connecting the ChipB35 and the LEADs 50 a-50 f.

[0005] The operation of the semiconductor integrated circuit device willnext be described.

[0006] The bonding wires 62 b and 62 d respectively connect the PADs 43a and 43 b of the Chip A20 to the LEADs 51 b and 51 d. The bonding wires61 a, 61 b, 61 c and 61 d respectively connect the PADs 42 a, 42 b, 42 cand 42 d of the Chip B35 to the LEADs 50 a, 50 c, 50 d and 50 e. Thebonding wire 60 d connects the PAD 40 d of the Chip A20 to the PAD 41 dof the Chip B35. Since these bonding wires 62 b, 62 d, 61 a, 61 b, 61 c,61 d and 60 d are those for connecting between the adjacent PADs andLEADs or between the adjacent PADs, they are not wired so as to straddlethe Chip A20 or the Chip B35.

[0007] On the other hand, the bonding wires 60 b and 60 e respectivelyconnect the PADs 40 b and 40 e of the Chip A20 to the LEADs 50 b and 50f, and the bonding wires 62 a and 62 f respectively connect the PADs 40a and 40 c of the Chip A20 to the LEADs 51 a and 51 f. Since thesebonding wires 60 b, 60 e, 62 a and 62 f are those for connecting betweennon-adjacent PADs and LEADs, they are wired so as to extend across theChip A20 or Chip B35.

[0008]FIG. 19 is a plan view showing a semiconductor integrated circuitdevice (related art example 2) of a conventional SIP (System In aPackage). In the drawing, reference numeral 16 indicates a bonding PAD,reference numeral 253 indicates a Chip A disposed on the bonding PAD16,and reference numeral 254 indicates a Chip B disposed on the bonding PAD16, respectively. Reference numerals 311 a-311 h and 311 p indicate PADsof the Chip A253, and reference numerals 312 i and 312 j indicate PADsof the Chip B254, respectively. Reference numerals 321 a, 321 c, 321 e,321 g, 321 i and 321 j respectively indicate signal LEADs disposedaround the bonding PAD 16, and reference numerals 322 b, 322 d, 322 f,322 h and 322 p respectively indicate power LEADs. Reference numerals361 a and 361 b indicate bonding PAD fixing LEADs respectively.Reference numerals 352 a-352 h, 353 i and 353 j indicate bonding wiresrespectively.

[0009] The operation of the semiconductor integrated circuit device willnext be explained.

[0010] The signal LEADs321 a, 321 c, 321 e, 321 g, 321 i and 321 j arerespectively connected to the PADs 311 a, 311 c, 311 e and 311 g of theChip A253 and the PADs312 i and 312 j of the Chip B254 by the bondingwires 352 a, 352 c, 352 e, 352 g, 353 i and 353 j. The power LEADs 322b, 322 d, 322 f, 322 h and 322 p are respectively connected to the PADs311 b, 311 d, 311 f, 311 h and 311 p of the Chip A253 by the bondingwires 352 b, 352 d, 352 f, 352 h and 352 p. The bonding PAD 16 is fixedby the bonding PAD fixing LEADs301 a and 361 b.

[0011] Since the PADs 311 b, 311 d, 311 f, 311 h and 311 p are connectedto their corresponding power LEADs 322 b, 322 d, 322 f, 322 h and 322 pand supplied with power, the power LEADs identical in number to the PADssupplied with the power are provided.

[0012] There arises a drawback in that since the conventionalsemiconductor integrated circuit device is constructed as describedabove, a further reduction in chip size where a plurality of chips aremounted, will cause a difficulty in connecting bonding wires betweenPADs of a chip and LEADs at positions where the PADs of the chip and theLEADs do not adjoin, when the number of the bonding wires is identicalor increases, thereby interfering with the reduction in chip size.

[0013] There also arises a drawback in that a further reduction in chipsize where a plurality of chips are mounted, will cause a difficulty insupplying stable power at positions where PADs of a chip and LEADs donot adjoin, when the number of bonding wires is identical or increases,thereby interfering with the reduction in chip size.

[0014] Further, there arises a drawback in that since a plurality ofchips are disposed adjacent to one another, the influence oftemperatures on the respective chips by heat generation of the chipscannot be avoided, and when a chip size is further reduced, thecondition of a chip-in temperature distribution must be confirmed fromthe need for taking into consideration the above influence oftemperatures on the respective chips.

SUMMARY OF THE INVENTION

[0015] This invention has been made to solve the foregoing drawbacks. Itis therefor an object of the present invention to obtain a semiconductorintegrated circuit device capable of easily and reliably connectingbonding wires between PADs and LEADs.

[0016] It is another object of the present invention to obtain asemiconductor integrated circuit device that ensures the supply ofstable power.

[0017] It is still another of the present invention to obtain asemiconductor integrated circuit device capable of confirming thecondition of a chip-in temperature distribution.

[0018] According to a first aspect of the present invention, there isprovided a semiconductor integrated circuit device including at leasttwo semiconductor integrated circuit chips respectively provided with aplurality of PADs, a plurality of LEADs disposed around arrays of thesemiconductor integrated circuit chips, and a plurality of bondingwires, wherein the plurality of bonding wires are connected so as not tostraddle one semiconductor integrated circuit chip and allow wiringbetween the PADs of the other integrated circuit chip and the LEADs.

[0019] Thus, wiring for long bonding wires extending across the onesemiconductor integrated circuit chip can be eliminated, and electricalconnections of the bonding wires between the PADs and LEADs are madeeasily and reliably.

[0020] According to a second aspect of the present invention, there isprovided a semiconductor integrated circuit device including asemiconductor integrated circuit chip provided with a plurality of PADs,a plurality of LEADs disposed around the semiconductor integratedcircuit chip, and two bonding wires for connecting one LEAD of theplurality of LEADs to the two PADs of the plurality of PADs.

[0021] Thus, since wiring is made between one LEAD and two PADs, thenumber of LEADs to be used can be reduced.

[0022] According to a third aspect of the present invention, there isprovided a semiconductor integrated circuit device including asemiconductor integrated circuit chip provided with a plurality of PADs,a plurality of LEADs disposed around the semiconductor integratedcircuit chip, and a bonding wire for connecting between power supplieslying within the semiconductor integrated circuit chip.

[0023] Thus, power enhancement can be made between the power supplies,and the area of a power supply wiring region can be reduced to diminishthe area of the semiconductor integrated circuit chip.

[0024] According to a fourth aspect of the present invention, there isprovided a semiconductor integrated circuit device including asemiconductor integrated circuit chip provided with a plurality of PADs,one or a plurality of LEADs disposed around an array of thesemiconductor integrated circuit chip, and a plurality of bonding wires.At least one LEAD of the plurality of LEADs is connected to two or morePADs of the plurality of PADs by the corresponding bonding wires of theplurality of bonding wires.

[0025] Thus, the plurality of PADs lying within a semiconductorintegrated circuit chip can be supplied with power.

[0026] According to a fifth aspect of the present invention, there isprovided a semiconductor integrated circuit device including asemiconductor integrated circuit chip provided with a plurality of PADs,and a plurality of temperature sensors for measuring a temperaturedistribution within the semiconductor integrated circuit chip.

[0027] Thus, a temperature distribution lying within the semiconductorintegrated circuit chip is recognized and estimated, thereby reducingthe size of the semiconductor integrated circuit chip.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028]FIG. 1 is a plan view showing a semiconductor integrated circuitdevice according to a first embodiment of the present invention;

[0029]FIG. 2 is a plan view illustrating a semiconductor integratedcircuit device according to a second embodiment of the presentinvention;

[0030]FIG. 3 is a plan view depicting a semiconductor integrated circuitdevice according to a third embodiment of the present invention;

[0031]FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. 3;

[0032]FIG. 5 is a cross-sectional view taken along line V-V of FIG. 3;

[0033]FIG. 6 is a plan view showing a semiconductor integrated circuitdevice according to a fourth embodiment of the present invention;

[0034]FIG. 7 is a cross-sectional view taken along line VII-VII of FIG.6;

[0035]FIG. 8 is a plan view illustrating a semiconductor integratedcircuit device according to a fifth embodiment of the present invention;

[0036]FIG. 9 is a cross-sectional view taken along IX-IX of FIG. 8;

[0037]FIG. 10 is a plan view showing a semiconductor integrated circuitdevice according to a sixth embodiment of the present invention;

[0038]FIG. 11 is a plan view depicting a semiconductor integratedcircuit device according to a seventh embodiment of the presentinvention;

[0039]FIG. 12 is a plan view illustrating a semiconductor integratedcircuit device according to an eighth embodiment of the presentinvention;

[0040]FIG. 13 is a plan view showing a semiconductor integrated circuitdevice according to a ninth embodiment of the present invention;

[0041]FIG. 14 is a plan view illustrating a semiconductor integratedcircuit device according to a tenth embodiment of the present invention;

[0042]FIG. 15 is a diagrammatic illustration of the semiconductorintegrated circuit device according to the tenth embodiment of thepresent invention;

[0043]FIG. 16 is a plan view showing a semiconductor integrated circuitdevice according to an eleventh embodiment of the present invention;

[0044]FIG. 17 is a plan view illustrating a semiconductor integratedcircuit device according to a twelfth embodiment of the presentinvention;

[0045]FIG. 18 is a plan view showing a semiconductor integrated circuitdevice (related art example 1) of a conventional SIP; and

[0046]FIG. 19 is a plan view illustrating a semiconductor integratedcircuit device (related art example 2) of a conventional SIP.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0047] An embodiment of the present invention will be described below.

[0048] First Embodiment

[0049]FIG. 1 is a plan view showing a semiconductor integrated circuitdevice according to a first embodiment of the present invention. In FIG.1, reference numeral 1 indicates a semiconductor integrated circuitdevice. Reference numeral 10 indicates a bonding pad (bonding PAD),reference numeral 20 indicates a semiconductor integrated circuit chip A(Chip A) disposed on the bonding PAD 10, and reference numeral 30indicates a semiconductor integrated circuit chip B (Chip B) includinginterface functions (I/F functions), which is disposed on the bondingPAD 10, respectively. Reference numerals 40 a-40 e indicate pads (PADs)of the Chip A20, and reference numerals 41 a-41 e and 42 a-42 d indicatepads (PADs) of the Chip B30, respectively. Reference numerals 50 a-50 dindicate leads (LEADs) disposed around arrays of the Chip A20 and ChipB30 disposed on the bonding PAD 10. Reference numerals 60 a-60 e and 61a-61 d respectively indicate bonding wires. Reference numeral 70 aindicates a wiring element which carries out the I/F function of theChip B30, reference numeral 70 b indicates a driver element whichperforms the I/F function of the Chip B30, reference numeral 70 cindicates a receiver element which performs the I/F function of the ChipB30, and reference numeral 70 d indicates a bidirectional buffer elementwhich carries out the I/F function of the Chip B30, respectively.

[0050] Electrical connections will next be described.

[0051] The PADs 40 a, 40 b, 40 c, 40 d and 40 e of the Chip A20 arerespectively connected to the PADs 41 a, 41 b, 41 c, 41 d and 41 e ofthe Chip B30 by the bonding wires 60 a, 60 b, 60 c, 60 d and 60 e. ThePADs 42 a, 42 b, 42 c and 42 d of the Chip B30 are respectivelyconnected to the LEAds50 a, 50 b, 50 c and 50 d by the bonding wires 61a, 61 b, 61 c and 61 d.

[0052] The wiring element 70 a, which carries out the I/F function, isconnected between the PAD 41 a and PAD 42 a of the Chip B30. The driverelement 70 b, which performs the I/F function, is connected between thePAD 41 b and PAD 42 c of the Chip B30. The receiver element 70 c, whichperforms the I/F function, is connected between the PAD 41 c and PAD 42b of the Chip B30. The bidirectional buffer element 70 d, which carriesout the I/F function, is connected between the PAD 41 d and PAD 41 e ofthe Chip B30 and the PAD 42 d thereof.

[0053] In the semiconductor integrated circuit device 1 according to thefirst embodiment, the Chip B30 including the I/F functions, is disposedbetween the Chip A20 and the LEADs 50 a through 50 d to wire between theChip A20 and the LEADs 50 a-50 d. When the PAD 40 a of the Chip A20 andthe LEAD 50 a are connected to each other, they are connected via thewiring element 70 a of the Chip B30. When the PAD 40 b of the Chip A20and the LEAD 50 c are connected to each other, they are connected viathe driver element 70 b of the Chip B30. When the PAD 40 c of the ChipA20 and the LEAD 50 b are connected to each other, they are connectedvia the receiver element 70 c of the Chip B30. When the PAD 40 d and PAD40 e of the Chip A20 and the LEAD50 d are connected to one another, theyare connected via the bidirectional buffer element 70 d of the Chip B30.

[0054] While the driver element 70 b and receiver element 70 c of theChip B30 are provided so as to intersect within the Chip B30 in FIG. 1,other wiring element 70 a and the bidirectional buffer element 70 d maybe provided so as to intersect other elements respectively. While thewiring element 70 a, the driver element 70 b, the receiver element 70 cand the bidirectional buffer element 70 d are provided as the I/Ffunctions one by one in FIG. 1, each of the I/F functions may compriseat least one type of element selected from a set comprising these fourtypes of elements.

[0055] The operation of the semiconductor integrated circuit device willnext be explained.

[0056] Since the PAD 40 a of the Chip A20 is connected to the LEAD50 athrough the wiring element 70 a of the Chip B30, the transfer of asignal between the PAD 40 a and the LEAD50 a (when the LEAD50 a is of asignal LEAD) or the supply of power therebetween (when the LEAD50 a isof a power LEAD) is performed.

[0057] Since the PAD 40 b of the Chip A20 is connected to the LEAD 50 cvia the driver element 70 b of the Chip B30, a signal outputted from thePAD 40 b is outputted to the LEAD 50 c through the driver element 70 b.

[0058] Since the PAD 40 c of the Chip A20 is connected to the LEAD50 bvia the receiver element 70 c of the Chip B30, a signal inputted to theLEAD50 b is inputted to the PAD 40 c through the receiver element 70 c.

[0059] Since the PAD 40 d and PAD 40 e of the Chip A20 are connected tothe LEAD50 d through the bidirectional buffer element 70 d of the ChipB30, a signal outputted from the PAD 40 d is outputted to the LEAD50 dthrough the bidirectional buffer element 70 d, whereas a signal inputtedto the LEAD50 d is inputted to the PAD 40 e via the bidirectional bufferelement 70 d.

[0060] As described above, the semiconductor integrated circuit device 1according to the first embodiment includes at least two semiconductorintegrated circuit chips (Chip A20 and Chip B30) respectively providedwith a plurality of PADs (PADs 40 a-40 e, 41 a-41 e and 42 a-42 d), aplurality of LEADs (LEADs 50 a-50 d) disposed around the arrays of thesemiconductor integrated circuit chips, and a plurality of bonding wires(bonding wires 60 a-60 e and 61 a-61 d). The plurality of bonding wiresare connected so as not to straddle one semiconductor integrated circuitchip (Chip B30) and allow wiring between the PADs (PADs 40 a-40 e) ofthe other semiconductor integrated circuit chip (Chip A20) and the LEADs(LEADs50-50 d).

[0061] Further, the semiconductor integrated circuit device 1 accordingto the first embodiment is configured such that one semiconductorintegrated circuit chip (Chip B30) has the I/F functions between theother semiconductor integrated circuit chip (Chip A20) and the LEADs(LEADs 50 a-50 d).

[0062] Furthermore, the semiconductor integrated circuit device 1according to the first embodiment is configured in such a manner thateach of the I/F functions includes at least one element selected fromthe set of the wiring element (70 a), driver element (70 b), receiverelement (70 c) and bidirectional buffer element (70 d).

[0063] According to the first embodiment as described above, anadvantageous effect is obtained in that since the Chip A20 and the LEADs50 a-50 d are connected to one another through the Chip B30 includingthe I/F functions, the electrical wiring of long bonding wires thatstraddle the Chip B30, can be eliminated, and the wires lying betweenthe Chip A20 and the LEADs 50 a-50 d can also be crossed each other.Further, an advantageous effect is obtained in that the Chip A20 and theLEADs 50 a-50 d can be connected to one another via the driver element70 b, receiver element 70 c and bidirectional buffer element 70 d.

[0064] Second Embodiment

[0065]FIG. 2 is a plan view showing a semiconductor integrated circuitdevice according to a second embodiment of the present invention. InFIG. 2, reference numeral 2 indicates a semiconductor integrated circuitdevice. Reference numeral 11 indicates a bonding pad (bonding PAD),reference numeral 21 indicates a semiconductor integrated circuit chip A(Chip A) disposed on the bonding PAD 11, reference numeral 80 indicatesa semiconductor integrated circuit chip (I/F Chip) including interfacefunctions (I/F functions), which is disposed on the bonding PAD 11, andreference numeral 31 indicates a semiconductor integrated circuit chip(Chip B) disposed between portions where the I/F functions of the I/Fchip80 are provided, respectively. Reference numerals 90 a-90 d indicatepads (PADs) of the Chip A21, reference numerals 91 a-91 d, 92 a-92 e, 95a-95 e and 96 a-96 d indicate pads (PADs) of the I/F Chip80, andreference numerals 93 a-93 e and 94 a-94 e indicate pads (PADs) of theChip B31, respectively. Reference numerals 100 a-100 d respectivelyindicate leads (LEADs) disposed around arrays of the Chip A21 and I/FChip 80 disposed on the bonding PAD 11. Reference numerals 110 a-110 d,111 a-111 e, 112 a-112 e, and 113 a-113 d indicate bonding wiresrespectively. Reference numerals 120 a and 121 a respectively indicatewiring elements which carry out I/F functions of the I/F Chip80.Reference numerals 120 b and 121 b respectively indicate driver elementswhich carry out I/F functions of the I/F Chip80. Reference numerals 120c and 121 c respectively indicate receiver elements which carry out I/Ffunctions of the I/F Chip80. Reference numerals 120 d and 121 drespectively indicate bidirectional buffer elements which carry out I/Ffunctions of the I/F Chip80.

[0066] Electrical connections will next be explained.

[0067] The PADs 90 a, 90 b, 90 c and 90 d of the Chip A21 arerespectively connected to the PADs 91 a, 91 b, 91 c and 91 d of the I/FChip80 by the bonding wires 110 a, 110 b, 110 c and 110 d. The PADs 92a, 92 b, 92 c, 92 d and 92 e of the I/F Chip80 are respectivelyconnected to the PADs 93 a, 93 b, 93 c, 93 d and 93 e of the Chip B31 bythe bonding wires 111 a, 111 b, 111 c, 111 d and 111 e. The PADs 94 a,94 b, 94 c, 94 d and 94 e of the Chip B31 are respectively connected tothe PADs 95 a, 95 b, 95 c, 95 d and 95 e of the I/F Chip80 by thebonding wires 112 a, 112 b, 112 c, 112 d and 112 e. The PADs 96 a, 96 b,96 c and 96 d of the I/F Chip80 are respectively connected to the LEADs100 a, 100 b, 100 c and 100 d by the bonding wires 113 a, 113 b, 113 cand 113 d.

[0068] The wiring elements 120 a and 121 a, which carry out the I/Ffunctions, are respectively connected between the PAD 91 a and PAD 92 aof the I/F Chip 80 and between the PAD 95 a and PAD 96 a thereof. Thereceiver element 120 c and the driver element 121 b, which carry out theI/F functions, are respectively connected between the PAD 91 b and PAD92 c of the I/F Chip 80 and between the PAD 95 b and PAD 96 c thereof.The driver element 120 b and the receiver element 121 c, which carry outthe I/F functions, are respectively connected between the PAD 91 c andPAD 92 b of the I/F Chip 80 and between the PAD 95 c and PAD 96 bthereof. The bidirectional buffer element 120 d and the bidirectionalbuffer element 121 d, which carry out the I/F functions, arerespectively connected between the PAD 91 d of the I/F Chip 80 and thePAD 92 d and PAD 92 e thereof, and between the PAD 95 d and PAD 95 e ofthe I/F chip 80 and the PAD 96 d thereof.

[0069] In the semiconductor integrated circuit device 2 according to thesecond embodiment, the I/F Chip 80 is disposed between the Chip A21 andthe LEADs 100 a-100 d, and the Chip B31 is placed on between portionswhere the I/F functions of the I/F Chip 80 are provided, in order towire between the Chip A21 and the Chip B31 and between the Chip B31 andthe LEADs 100 a-100 d. When the PAD 90 a of the Chip A21 and the PAD 93a of the Chip B31 are connected to each other, they are connected viathe wiring element 120 a of the I/F Chip 80. When the PAD 94 a of theChip B31 and the LEAD 100 a are connected to each other, they areconnected via the wiring element 121 a of the I/F Chip 80. When the PAD90 b of the Chip A21 and the PAD 93 c of the Chip B31 are connected toeach other, they are connected via the receiver element 120 c of the I/FChip 80. When the PAD 94 b of the Chip B31 and the LEAD 100 c areconnected to each other, they are connected via the driver element 121 bof the I/F Chip 80. When the PAD 90 c the Chip A21 and the PAD 93 b ofthe Chip B31 are connected to each other, they are connected via thedriver element 120 b of the I/F Chip 80. When the PAD 94 c of the ChipB31 and the LEAD 100 b are connected to each other, they are connectedvia the receiver element 121 c of the I/F Chip 80. When the PAD 90 d ofthe Chip A21 and the PAD 93 d and PAD 93 e of the Chip B31 are connectedto one another, they are connected via the bidirectional buffer element120 d of the I/F Chip80. When the PAD 94 d and PAD 94 e of the Chip B31and the LEAD 100 d are connected to one another, they are connected viathe bidirectional buffer element 121 d of the I/F Chip 80.

[0070] While the driver element 120 b and receiver element 120 c of theI/F Chip 80, and the driver element 121 b and receiver element 121 cthereof are respectively provided so as to intersect one another withinthe I/F Chip 80 in FIG. 2, other wiring elements 120 a and 121 a andbidirectional buffer elements 120 d and 121 d may be provided so as tointersect other elements respectively. Further, while the wiringelements 120 a and 121 a, the driver elements 120 b and 121 b, thereceiver elements 120 c and 121 c and the bidirectional buffer elements120 d and 121 d are respectively provided as the I/F functions in FIG.2, each of the I/F functions may comprise at least one type of elementselected from a set comprising these four types of elements.

[0071] The operation of the semiconductor integrated circuit device willnext be described.

[0072] Since the PAD 94 a of the Chip B31 is connected to itscorresponding LEAD 100 a via the wiring element 121 a of the I/F Chip80, the transfer of a signal between the PAD 94 a and the LEAD 100 a(when the LEAD 100 a is of a signal LEAD) or the supply of powertherebetween (when the LEAD 100 a is of a power LEAD) is performed.

[0073] Since the PAD 94 b of the Chip B31 is connected to itscorresponding LEAD 100 c via the driver element 121 b of the I/F Chip80, a signal outputted from the PAD 94 b is outputted to the LEAD100 cthrough the driver element 121 b.

[0074] Since the PAD 94 c of the Chip B31 is connected to itscorresponding LEAD 100 b via the receiver element 121 c of the I/Fchip80, a signal inputted to the LEAD 100 b is inputted to the PAD 94 cthrough the receiver element 121 c.

[0075] Since the PAD 94 d and PAD 94 e of the Chip B31 are connected totheir corresponding LEAD 100 d via the bidirectional buffer element 121d of the I/F Chip 80, a signal outputted from the PAD 94 d is outputtedto the LEAD 100 d through the bidirectional buffer element 121 d,whereas a signal inputted to the LEAD 100 d is inputted to the PAD 94 ethrough the bidirectional buffer element 121 d.

[0076] Since the PAD 93 a of the Chip B31 is connected to itscorresponding PAD 90 a of the Chip A21 via the wiring element 120 a ofthe I/F Chip 80, the transfer of a signal between the PAD 93 a and thePAD 90 a (when the PAD 93 a is of a signal PAD) or the supply of powertherebetween (when the PAD 93 a is of a power PAD) is performed.

[0077] Since the PAD 93 b of the Chip B31 is connected to itscorresponding PAD 90 c of the Chip A21 via the driver element 120 b ofthe I/F Chip80, a signal outputted from the PAD 93 b is supplied to thePAD 90 c through the driver element 120 b.

[0078] Since the PAD 93 c of the Chip B31 is connected to itscorresponding PAD 90 b of the Chip A21 via the receiver element 120 c ofthe I/F Chip 80, a signal outputted from the PAD 90 b is supplied to thePAD 93 c through the receiver element 120 c.

[0079] Since the PAD 93 d and PAD 93 e of the Chip B31 are connected totheir corresponding PAD 90 d of the Chip A21 via the bidirectionalbuffer element 120 d of the I/F Chip 80, a signal outputted from the PAD93 d is supplied to the PAD 90 d through the bidirectional bufferelement 120 d, whereas a signal outputted from the PAD 90 d is suppliedto the PAD 93 e through the bidirectional buffer element 120 d.

[0080] As described above, the semiconductor integrated circuit device 2according to the second embodiment includes two semiconductor integratedcircuit chips (Chip A21 and Chip B31) respectively provided with aplurality of PADs (PADs 90 a-90 d, PADs 93 a-93 e and PADs 94 a-94 e), aplurality of LEADs (LEADs 100 a-100 d) disposed around the arrays of thesemiconductor integrated circuit chips, and a plurality of bonding wires(bonding wires 111 a-111 e, 112 a-112 e and 113 a-113 d). The pluralityof bonding wires are connected so as not to straddle one semiconductorintegrated circuit chip (Chip B31) and allow wiring between the PADs(PADs 90 a-90 d) of the other semiconductor integrated circuit chip(Chip A21) and the LEADs (LEADs 100 a-100 d).

[0081] Further, the semiconductor integrated circuit device 2 accordingto the second embodiment has also a third semiconductor integratedcircuit chip (I/F Chip 80) provided with a plurality of PADs (PADs 91a-91 d, 92 a-92 e, 95 a-95 e and 96 a-96 d). The third semiconductorintegrated circuit chip (I/F Chip 80) has the I/F functions between theother semiconductor integrated circuit chip (Chip A21) and the onesemiconductor integrated circuit chip (Chip B31) and the I/F functionsbetween the one semiconductor integrated circuit chip (Chip B31) and theLEADs (LEADs 100 a-100 d).

[0082] Furthermore, the semiconductor integrated circuit device 2according to the second embodiment is configured in such a manner thateach of the I/F functions includes at least one element selected fromthe set of the wiring elements (120 a and 121 a), driver elements (120 band 121 b), receiver elements (120 c and 121 c) and bidirectional bufferelements (120 d and 121 d).

[0083] According to the second embodiment as described above, anadvantageous effect is obtained in that since the Chip A21 and the ChipB31, and the Chip B31 and the LEADs 100 a-100 d are respectivelyconnected to one another through the I/F Chip 80 including the I/Ffunctions, the electrical wiring of long bonding wires that straddle theChip B31, can be eliminated when the Chip A21 and the LEADs 100 a-100 dare connected, and the wires lying between the Chip A21 and the LEADs100 a-100 d can also be crossed each other. An advantageous effect isalso obtained in that the Chip A21 and the LEADs 100 a-100 d can beconnected to one another via the driver elements 120 b and 121 b,receiver elements 120 c and 121 c and bidirectional buffer elements 120d and 121 d. Further, when the Chip B31 and the Chip A21 are connectedto each other, and the Chip B31 and the LEADs 100 a-100 d are connected,the electrical wiring of long bonding wires that extend across the I/FChip 80, can be eliminated, and the wires lying between the Chip B31 andthe Chip A21 and between the Chip B31 and the LEADs 100 a-100 d can alsobe crossed one another. Furthermore, an advantageous effect is obtainedin that the Chip B31 and the Chip A21, and the Chip B31 and the LEADs100 a-100 d can respectively be connected to one another via the driverelements 120 b and 121 b, receiver elements 120 c and 121 c andbidirectional buffer elements 120 d and 121 d.

[0084] Third Embodiment

[0085]FIG. 3 is a plan view showing a semiconductor integrated circuitdevice according to a third embodiment of the present invention. FIG. 4is a cross-sectional view taken along line IV-IV of FIG. 3, and FIG. 5is a cross-sectional view taken along line V-V of FIG. 3, respectively.In FIG. 4, reference numeral 3 indicates a semiconductor integratedcircuit device. Reference numeral 12 indicates a bonding pad (bondingPAD), reference numeral 22 indicates a semiconductor integrated circuitchip A (Chip A) disposed on the bonding PAD 12, reference numeral 81indicates an I/F semiconductor integrated circuit chip (I/F Chip)including interface functions (I/F functions), which is disposed on thebonding PAD 12, reference numeral 32 indicates a semiconductorintegrated circuit chip B (Chip B) disposed on the I/F chip 81, andreference numeral 130 indicates a height adjusting semiconductorintegrated circuit chip (height adjustment Chip) including interfacefunctions (I/F functions), which is disposed on the I/F chip 81,respectively. Reference numerals 140 a-140 j indicate pads (PADs) of theChip A22, reference numerals 141 a-141 e and 142 a-142 d indicate pads(PADs) of the height adjustment Chip130, and reference numerals 141f-141 j and 142 f-142 j indicate pads (PADs) of the Chip B32,respectively. Reference numerals 150 a-150 d and 150 f-150 jrespectively indicate leads (LEADs) disposed around arrays of the ChipA22 and I/F Chip81 disposed on the bonding PAD12. Reference numerals 160a-160 j, 161 a-161 d, and 161 f-161 j indicate bonding wiresrespectively. Reference numeral 170 a indicates a wiring element whichcarries out an I/F function of the height adjusting Chip130. Referencenumeral 170 b indicates a driver element which carries out an I/Ffunction of the height adjusting Chip130. Reference numeral 170 cindicates a receiver element which carries out an I/F function of theheight adjusting Chip130. Reference numeral 170 d indicates abidirectional buffer element which carries out an I/F function of theheight adjusting Chip130.

[0086] Electrical connections will next be explained.

[0087] The PADs 140 a, 140 b, 140 c, 140 d and 140 e of the Chip A22 arerespectively connected to the PADs 141 a, 141 b, 141 c, 141 d and 141 eof the height adjusting Chip130 by the bonding wires 160 a, 160 b, 160c, 160 d and 160 e. The PADs 142 a, 142 b, 142 c and 142 d of the heightadjusting Chip130 are respectively connected to the LEADs 150 a, 150 b,150 c and 150 d by the bonding wires 161 a, 161 b, 161 c and 161 d. ThePADs 141 a-141 e and 142 a-142 d of the height adjusting Chip130 arerespectively disposed at such heights as to be provided flush with thePADs 140 a-140 e of the Chip A22. The PADs 140 f, 140 g, 140 h, 140 iand 140 j of the Chip A22 are respectively connected to the PADs 141 f,141 g, 141 h, 141 i and 141 j of the Chip B32 by the bonding wires 160f, 160 g, 160 h, 160 i and 160 j. The PADs 142 f, 142 g, 142 h, 142 iand 142 j of the Chip B32 are respectively connected to the LEADs 150 f,150 g, 150 h, 150 i and 150 j by the bonding wires 161 f, 161 g, 161 h,161 i and 161 j.

[0088] The wiring element 170 a, which carries out the I/F function, isconnected between the PAD 141 a and PAD 142 a of the height adjustingChip 130. The driver element 170 b, which effects the I/F function, isconnected between the PAD 141 b and PAD 142 c of the height adjustingChip 130. The receiver element 170 c, which carries out the I/Ffunction, is connected between the PAD 141 c and PAD 142 b of the heightadjusting Chip 30. The bidirectional buffer element 170 d, which carriesout the I/F function, is connected between the PAD 141 d and PAD 141 eof the height adjusting Chip 130 and the PAD 142 d thereof.

[0089] In the semiconductor integrated circuit device 3 according to thethird embodiment, the height adjusting I/F Chip 130 is disposed on theI/F Chip 81 placed between the Chip A22 and the LEADs 150 a-150 d inorder to wire between the Chip A22 and the LEADs 150 a-150 d. Further,the Chip B32 is placed at a portion where the height adjusting I/F Chip130 of the I/F Chip 81 is not disposed. When the PAD 140 a of the ChipA22 and the LEAD 150 a are connected to each other, they are connectedvia the wiring element 170 a of the height adjusting I/F Chip 130. Whenthe PAD 140 b of the Chip A22 and the LEAD 150 c are connected to eachother, they are connected via the driver element 170 b of the heightadjusting I/F Chip 130. When the PAD 140 c of the Chip A22 and the LEAD150 b are connected to each other, they are connected via the receiverelement 170 c of the height adjusting I/F Chip130. When the PAD 140 dand PAD 140 e of the Chip A22 and the LEAD 150 d are connected to oneanother, they are connected via the bidirectional buffer element 170 dof the height adjusting I/F Chip 130.

[0090] While the driver element 170 b and receiver element 170 c of theheight adjusting I/F Chip 130 are provided so as to intersect each otherwithin the height adjusting I/F Chip 130 in FIG. 3, other wiring element170 a and bidirectional buffer element 170 d may be provided so as tointersect other elements respectively. Further, while the wiring element170 a, driver element 170 b, receiver element 170 c and bidirectionalbuffer element 170 d are provided one by one as the I/F functions inFIG. 3, each of the I/F functions may comprise at least one type ofelement selected from a set comprising these four types of elements.

[0091] The operation of the semiconductor integrated circuit device willnext be described.

[0092] Since the PAD 140 a of the Chip A22 is connected to itscorresponding LEAD 150 a via the wiring element 170 a of the heightadjusting I/F Chip 130, the transfer of a signal between the PAD 140 aand the LEAD 150 a (when the LEAD 150 a is of a signal LEAD) or thesupply of power therebetween (when the LEAD 150 a is of a power LEAD) isperformed.

[0093] Since the PAD 140 b of the Chip A22 is connected to itscorresponding LEAD 150 c via the driver element 170 b of the heightadjusting I/F Chip 130, a signal outputted from the PAD 140 b isoutputted to the LEAD 150 c through the driver element 170 b.

[0094] Since the PAD 140 c of the Chip A22 is connected to itscorresponding LEAD150 b via the receiver element 170 c of the heightadjusting I/F chip 130, a signal inputted to the LEAD150 b is inputtedto the PAD 140 c through the receiver element 170 c.

[0095] Since the PAD 140 d and PAD 140 e of the Chip A22 are connectedto their corresponding LEAD 150 d via the bidirectional buffer element170 d of the height adjusting I/F Chip 130, a signal outputted from thePAD 140 d is outputted to the LEAD 150 d through the bidirectionalbuffer element 170 d, whereas a signal inputted to the LEAD 150 d isinputted to the PAD 140 e through the bidirectional buffer element 170d.

[0096] As described above, the semiconductor integrated circuit device 3according to the third embodiment includes two semiconductor integratedcircuit chips (Chip A22 and Chip B32) respectively provided with aplurality of PADs (PADs 140 a-140 j, 141 f-141 j, and 142 f-142 j), aplurality of LEADs (LEADs 150 a-150 j) disposed around the arrays of thesemiconductor integrated circuit chips, and a plurality of bonding wires(bonding wires 160 a-160 j, 161 a-161 d and 161 f-161 j). The pluralityof bonding wires are connected so as not to straddle or extend acrossone semiconductor integrated circuit chip (Chip B32) and allow wiringbetween the PADs (PADs 140 a-140 j) of the other semiconductorintegrated circuit chip (Chip A22) and the LEADs (LEADs 150 a-150 d).

[0097] Further, the semiconductor integrated circuit device 3 accordingto the third embodiment has also a third semiconductor integratedcircuit chip (I/F Chip 81) disposed under the one semiconductorintegrated circuit chip (Chip B32), and a height adjusting semiconductorintegrated circuit chip (height adjusting Chip 130) provided with aplurality of PADs (PADs 141 a-141 e and 142 a-142 d), which is disposedon the third semiconductor integrated circuit chip (I/F Chip 81) so asto adjoin the one semiconductor integrated circuit chip (Chip B32). Theheight adjusting semiconductor integrated circuit chip (height adjustingChip 130) has the I/F functions between the other semiconductorintegrated circuit chip (Chip A22) and the LEADs (LEADs 150 a-150 d).The plurality of PADs (PADs 141 a-141 e and 142 a-142 d) of the heightadjusting semiconductor integrated circuit chip (height adjustingChip130) are respectively disposed on the same plane as the plurality ofPADs (PADs 140 a-140 j) of the other semiconductor integrated circuitchip (Chip A22).

[0098] Furthermore, the semiconductor integrated circuit device 3according to the third embodiment is configured in such a manner thateach of the I/F functions includes at least one element selected fromthe set of the wiring element (170 a), driver element (170 b), receiverelement (170 c) and bidirectional buffer element (170 d).

[0099] According to the third embodiment as described above, anadvantageous effect is obtained in that since the Chip A22 and LEADs 150a-150 d are connected via the height adjusting Chip130 including the I/Ffunctions, which is disposed on the I/F Chip 81, adjacent to the ChipB32, the electrical wiring of long bonding wires that extend across theChip B32, can be eliminated when the Chip A22 and the LEADs 150 a-150 dare connected, and the wires lying between the Chip A22 and the LEADs150 a-150 d can also be crossed each other. An advantageous effect isalso obtained in that the Chip A22 and the LEADs 150 a-150 d can beconnected to one another via the driver element 170 b, receiver element170 c and bidirectional buffer element 170 d. Further, an advantageouseffect is obtained in that since the PADs 141 a-141 e and 142 a-142 d ofthe height adjusting Chip 130 are disposed flush with the PADs 140 a-140j of the Chip A22, wiring can easily be carried out.

[0100] Fourth Embodiment

[0101]FIG. 6 is a plan view showing a semiconductor integrated circuitdevice according to a fourth embodiment of the present invention. FIG. 7is a cross-sectional view taken along line VII-VII of FIG. 6 and alsoshows elements of structure or components which appear in across-section taken along line VIIa-VIIa of FIG. 6 to intelligibly showa structure of the semiconductor integrated circuit device. In FIG. 6,reference numeral 4 indicates a semiconductor integrated circuit device.Reference numeral 13 indicates a bonding pad (bonding PAD), referencenumeral 23 indicates a semiconductor integrated circuit chip A (Chip A)disposed on the bonding PAD 13, reference numeral 82 indicates asemiconductor integrated circuit chip (I/F Chip) including interfacefunctions (I/F functions), which is disposed on the bonding PAD 13, andreference numeral 33 indicates a semiconductor integrated circuit chip B(Chip B) disposed on the I/F Chip 82, respectively. Reference numerals180 a-180 h indicate pads (PADs) of the Chip A23, reference numerals 181a, 181 c, 181 e, 181 g, 181 h, 184 a, 184 c, 184 e and 184 g indicatepads (PADs) of the I/F Chip 82, and reference numerals 182 b, 182 d, 182f, 183 b, 183 d and 183 f indicate pads (PADs) of the Chip B33,respectively. Reference numerals 190 a-190 g respectively indicate leads(LEADs) disposed around arrays of the Chip A23 and I/F Chip 82 disposedon the bonding PAD 13. Reference numerals 200 a-200 h and 201 a-201 gindicate bonding wires respectively. Reference numeral 210 a indicates awiring element which carries out an I/F function of the I/F Chip 82.Reference numeral 210 b indicates a driver element which carries out anI/F function of the I/F Chip 82. Reference numeral 210 c indicates areceiver element which carries out an I/F function of the I/F Chip 82.Reference numeral 210 d indicates a bidirectional buffer element whichcarries out an I/F function of the I/F Chip 82.

[0102] Electrical connections will next be explained.

[0103] The PADs 180 a, 180 c, 180 e, 180 g and 180 h of the Chip A23 arerespectively connected to the PADs 181 a, 181 c, 181 e, 181 g and 181 hof the I/F Chip 82 by the bonding wires 200 a, 200 c, 200 e, 200 g and200 h. The PADs 180 b, 180 d and 180 f of the Chip A23 are respectivelyconnected to the PADs 182 b, 182 d and 182 f of the Chip B33 by thebonding wires 200 b, 200 d and 200 f. The PADs 184 a, 184 c, 184 e and184 g of the I/F Chip82 are respectively connected to the LEADs 190 a,190 c, 190 e and 190 g by the bonding wires 201 a, 201 c, 201 e and 201g. The PADs 183 b, 183 d and 183 f of the Chip B33 are respectivelyconnected to the LEADs 190 b, 190 d and 190 f by the bonding wires 201b, 201 d and 201 f.

[0104] The wiring element 210 a, which carries out the I/F function, isconnected between the PAD 181 a and PAD 184 a of the I/F Chip 82. Thedriver element 210 b, which effects the I/F function, is connectedbetween the PAD 181 c and PAD 184 e of the I/F Chip 82. The receiverelement 210 c, which carries out the I/F function, is connected betweenthe PAD 181 e and PAD 184 c of the I/F Chip82. The bidirectional bufferelement 210 d, which carries out the I/F function, is connected betweenthe PAD 181 g and PAD 181 h of the I/F Chip 82 and the PAD 184 gthereof.

[0105] In the semiconductor integrated circuit device 4 according to thefourth embodiment, the I/F Chip 82 is disposed under the Chip B33 placedbetween the Chip A23 and the LEADs 190 a-190 g in order to wire betweenthe Chip A23 and the LEADs 190 a-190 g. When the PAD 180 a of the ChipA23 and the LEAD 190 a are connected to each other, they are connectedvia the wiring element 210 a of the I/F Chip 82. When the PAD 180 c ofthe Chip A23 and the LEAD 190 e are connected to each other, they areconnected via the driver element 210 b of the I/F Chip 82. When the PAD180 e of the Chip A23 and the LEAD 190 c are connected to each other,they are connected via the receiver element 210 c of the I/F Chip 82.When the PAD 180 g and PAD 180 h of the Chip A23 and the LEAD 190 g areconnected to one another, they are connected via the bidirectionalbuffer element 210 d of the I/F Chip 82.

[0106] While the driver element 210 b and receiver element 210 c of theI/F Chip 82 are provided so as to intersect each other within the I/FChip 82 in FIG. 6, other wiring element 210 a and bidirectional bufferelement 210 d may be provided so as to intersect other elementsrespectively. Further, while the wiring element 210 a, driver element210 b, receiver element 210 c and bidirectional buffer element 210 d areprovided one by one as the I/F functions in FIG. 6, each of the I/Ffunctions may comprise at least one type of element selected from a setcomprising these four types of elements.

[0107] The operation of the semiconductor integrated circuit device willnext be described.

[0108] Since the PAD 180 a of the Chip A23 is connected to itscorresponding LEAD 190 a via the wiring element 210 a of the I/F Chip82, the transfer of a signal between the PAD 180 a and the LEAD 190 a(when the LEAD 190 a is of a signal LEAD) or the supply of powertherebetween (when the LEAD 190 a is of a power LEAD) is performed.

[0109] Since the PAD 180 c of the Chip A23 is connected to itscorresponding LEAD 190 e via the driver element 210 b of the I/F Chip82, a signal outputted from the PAD 180 c is outputted to the LEAD190 ethrough the driver element 210 b.

[0110] Since the PAD 180 e of the Chip A23 is connected to itscorresponding LEAD 190 c via the receiver element 210 c of the I/FChip82, a signal inputted to the LEAD 190 c is inputted to the PAD 180 ethrough the receiver element 210 c.

[0111] Since the PAD 180 g and PAD 180 h of the Chip A23 are connectedto their corresponding LEAD 190 g via the bidirectional buffer element210 d of the I/F Chip 82, a signal outputted from the PAD 180 g isoutputted to the LEAD 190 g through the bidirectional buffer element 210d, whereas a signal inputted to the LEAD 190 g is inputted to the PAD180 h through the bidirectional buffer element 210 d.

[0112] As described above, the semiconductor integrated circuit device 4according to the fourth embodiment includes two semiconductor integratedcircuit chips (Chip A23 and Chip B33) respectively provided with aplurality of PADs (PADs 180 a-180 h, 182 b, 182 d, 182 f, 183 b, 183 dand 183 f), a plurality of LEADs (LEADs 190 a-190 g) disposed around thearrays of the semiconductor integrated circuit chips, and a plurality ofbonding wires (bonding wires 200 a-200 h, and 201 a-201 g). Theplurality of bonding wires (bonding wires 200 a-200 h and 201 a-201 g)are connected so as not to straddle or extend across one semiconductorintegrated circuit chip (Chip B33) and allow wiring between the PADs(PADs 180 a-180 h) of the other semiconductor integrated circuit chip(Chip A23) and the LEADs (LEADs 190 a-190 g).

[0113] Further, the semiconductor integrated circuit device 4 accordingto the fourth embodiment also has an I/F semiconductor integratedcircuit chip (I/F Chip 82) provided with a plurality of PADs (PADs 181a, 181 c, 181 e, 181 g, 181 h, 184 a, 184 c, 184 e and 184 g), which isdisposed under the one semiconductor integrated circuit chip (Chip B33).The I/F semiconductor integrated circuit chip (I/F Chip82) has the I/Ffunctions between the other semiconductor integrated circuit chip (ChipA23) and the LEADs (LEADs 190 a-190 g).

[0114] Furthermore, the semiconductor integrated circuit device 4according to the fourth embodiment is configured in such a manner thateach of-the I/F functions includes at least one element selected fromthe set of the wiring element (210 a), driver element (210 b), receiverelement (210 c) and bidirectional buffer element (210 d).

[0115] According to the fourth embodiment as described above, anadvantageous effect is obtained in that since the Chip A23 and the LEADs190 a-190 g are connected to one another via the I/F Chip82 includingthe I/F functions, which is disposed under the Chip B33, the electricalwiring of long bonding wires that extend across the Chip B33, can beeliminated where the Chip A23 and the LEADs 190 a-190 g are connected,and the wires lying between the Chip A23 and the LEADs 190 a-190 g canalso be crossed each other. An advantageous effect is also obtained inthat the Chip A23 and the LEADs 190 a-190 g can be connected to oneanother via the driver element 210 b, receiver element 210 c andbidirectional buffer element 210 d. Further, an advantageous effect isobtained in that since the I/F Chip82 including the I/F functions isplaced under the Chip B33, the area of the whole semiconductorintegrated circuit device of SIP can be reduced.

[0116] Fifth Embodiment

[0117]FIG. 8 is a plan view showing a semiconductor integrated circuitdevice according to a fifth embodiment of the present invention. FIG. 9is a cross-sectional view taken along line IX-IX of FIG. 8 and alsoshows elements of structure or components which appear in cross-sectionstaken along line IXa-IXa and line IXb-IXb of FIG. 8 to intelligiblyindicate a structure of the semiconductor integrated circuit device. InFIG. 8, reference numeral 5 indicates a semiconductor integrated circuitdevice. Reference numeral 14 indicates a bonding pad (bonding PAD),reference numeral 24 indicates a semiconductor integrated circuit chip A(Chip A) disposed on the bonding PAD 14, and reference numeral 34indicates a semiconductor integrated circuit chip B (Chip B) disposed onthe bonding PAD 14, respectively. Reference numerals 220 a-220 dindicate pads (PADs) of the Chip A, and reference numerals 221 b and 222b indicate pads (PADs) of the Chip B34, respectively. Reference numerals230 a-230 d respectively indicate leads (LEADs) disposed around arraysof the Chip A24 and Chip B34 disposed on the bonding PAD 14. Referencenumerals 240 a-240 d and 241 b indicate bonding wires respectively. TheLEADs 230 c and 230 d extend under the Chip B34 and reach theircorresponding positions adjacent to the Chip A24.

[0118] Electrical connections will next be explained.

[0119] The PAD 220 a of the Chip A24 is connected to the LEAD 230 a bythe bonding wire 240 a. Since the connection therebetween by the bondingwire 240 a straddles the Chip B34, this is not a structure intended forthe semiconductor integrated circuit device of the invention. However,it has been shown for comparison with the characteristics of a structureof the fifth embodiment to be described later. The PAD 220 b of the ChipA24 is connected to its corresponding PAD 221 b of the Chip B34 by thebonding wire 240 b. The PADs 220 c and 220 d of the Chip A24 arerespectively connected to the LEADs 230 c and 230 d by the bonding wires240 c and 240 d.

[0120] In the semiconductor integrated circuit device according to thefifth embodiment, the PADs 220 c and 220 d of the Chip A24 arerespectively connected to the LEADs 230 c and 230 d by the bonding wires240 c and 240 d, which LEADs extend under the Chip B34 and reach thepositions adjacent to the Chip A24. Thus, since the LEADs 230 c and 230d extend under the Chip B34 and reach the positions adjacent to the ChipA24, the bonding wires 240 c and 240 d can be wired without extendingacross the Chip B34 as in the case of the bonding wire 240 a forconnecting the PAD 220 a to the LEAD 230 a.

[0121] The operation of the semiconductor integrated circuit device willnext be described.

[0122] Since the PAD 220 b of the Chip A24 is connected to the PAD 221 bof the Chip B34 by the bonding wire 240 b, the transfer of a signal orthe supply of power is performed between the PAD 220 b and the PAD 221b. Since the PAD 220 c of the Chip A24 is connected to it correspondingLEAD 230 c by the bonding wire 240 c, the transfer of a signal isperformed between the PAD 220 c and the LEAD 230 c (where the LEAD 230 cis of a signal LEAD) or the supply of power is performed therebetween(where the LEAD 230 c is of a power LEAD). Since the PAD 220 d of theChip A24 is connected to its corresponding LEAD230 d by the bonding wire240 d, the transfer of a signal is performed between the PAD 220 d andthe LEAD 230 d (when the LEAD 230 d is of a signal LEAD) or the supplyof power is performed therebetween (when the LEAD 230 d is of a powerLEAD). Since the PAD 222 b of the Chip B34 is connected to itscorresponding LEAD 230 b by the bonding wire 241 b, the transfer of asignal is performed between the PAD 222 b and the LEAD 230 b (when theLEAD230 b is of a signal LEAD) or the supply of power is performedtherebetween (when the LEAD230 b is of a power LEAD).

[0123] As described above, the semiconductor integrated circuit device 5according to the fifth embodiment includes two semiconductor integratedcircuit chips (Chip A24 and Chip B34) respectively provided with aplurality of PADs (PADs 220 a-220 d, 221 b and 222 b), a plurality ofLEADs (LEADs 230 a-230 d) disposed around the arrays of thesemiconductor integrated circuit chips, and a plurality of bonding wires(bonding wires 240 b-240 d, and 241 b). The plurality of bonding wires(bonding wires 240 b-240 d and 241 b) are connected so as not tostraddle or extend across one semiconductor integrated circuit chip(Chip B34) and allow wiring between the PADs (PADs220 b-220 d) of theother semiconductor integrated circuit chip (Chip A24) and the LEADs(LEADs 230 b-230 d).

[0124] Further, the semiconductor integrated circuit device 5 accordingto the fifth embodiment includes LEADs which extend under the onesemiconductor integrated circuit chip (Chip B34) and reach theircorresponding positions adjacent to the other semiconductor integratedcircuit chip (Chip A24).

[0125] According to the fifth embodiment as described above, anadvantageous effect is obtained in that since there are provided theLEADs which extend under the Chip B34 and reach the positions adjacentto the Chip A24, wiring between the Chip A24 and the LEADs can beperformed in the shortest form.

[0126] Sixth Embodiment

[0127]FIG. 10 is a plan view showing a semiconductor integrated circuitdevice according to the sixth embodiment of the present invention. InFIG. 10, reference numeral 6 indicates a semiconductor integratedcircuit device, and reference numeral 250 indicates a semiconductorintegrated circuit chip (Chip). Reference numerals 260 a-260 d indicatepads (PADs) of the Chip 250, and reference numerals 270 a-270 d indicateLEADs (LEAD) disposed around the Chip250. Reference numerals 280 a and280 b indicate bonding wires. Reference numeral 290 indicates an ammeterwith a dc power supply (not shown) provided thereinside. Referencenumerals 300 a, 300 b and 300 c indicate chip-in wires of the Chip 250.

[0128] Electrical connections will next be described.

[0129] The PAD 260 a and PAD 260 b of the Chip 250 are respectivelyconnected to the LEAD 270 b by the bonding wires 280 a and 280 b. ThePAD 260 a is connected to the PAD 260 d by the chip-in wire 300 b. ThePAD 260 b is connected to the PAD 260 c by the chip-in wire 300 c. ThePAD 260 a and PAD 260 b are connected to each other by the chip-in wire300 a. The ammeter 290 is connected between the PAD 260 c and the PAD260 d.

[0130] While the PAD 260 a and PAD 260 b are connected to each other bythe chip-in wire 300 a in the semiconductor integrated circuit deviceshown in FIG. 10, they may not be connected to each other by the chip-inwire 300 a. While the ammeter 290 is connected between the PAD 260 dconnected to the PAD 260 a by the chip-in wire 300 b and the PAD 260 cconnected to the PAD 260 b by the chip-in wire 300 c, it may be directlyconnected between the PAD 260 a and the PAD 260 b.

[0131] The operation of the semiconductor integrated circuit device willnext be described.

[0132] Since the PAD 260 a and PAD 260 b of the Chip 250 arerespectively connected to the LEAD 270 b by the bonding wire 280 a andthe bonding wire 280 b, the transfer of signals is performed between thePAD 260 a and the LEAD 270 b and between the PAD 260 b and the LEAD 270b (when the LEAD 270 b is of a signal LEAD) or the supply of power isperformed therebetween (when the LEAD 270 b is of a power LEAD).

[0133] A connection test executed by the ammeter 290 in the sixthembodiment is based on the following principle.

[0134] Firstly, when both the PAD 260 a and PAD 260 b are connected tothe LEAD 270 b, paths along which currents measured by the ammeter 290flow, may include two paths: a first path which extends from the PAD 260d to the PAD 260 c via the chip-in wire 300 b, the chip-in wire 300 a(and unillustrated other chip-in wires between the PAD 260 a and the PAD260 b) and the chip-in wire 300 c, and a second path which extends fromthe PAD 260 d to the PAD 260 c via the chip-in wire 300 b, the PAD 260a, the bonding wire 280 a, the LEAD 270 b, the bonding wire 280 b, thePAD 260 b and the chip-in wire 300 c.

[0135] Next, when either or both of the PAD 260 a and PAD 260 b aredisconnected from the LEAD 270 b, only the first path referred to aboveis taken as the path along which the current measured by the ammeter 290flows. Thus, as compared with the case where the currents flow in boththe first path and the second path (i.e., where both the PAD 260 a andPAD 260 b are connected to the LEAD 270 b), the resistance value of thepath along which the current flows, increases and hence the value of thecurrent is reduced.

[0136] Thus, a current value at the time that both the PAD 260 a and PAD260 b are connected to the LEAD 270 b, is regarded as a normal value.Further, when the current value is relatively lower than the normalvalue, the electrical connection between the PAD 260 a and PAD 260 b andthe LEAD 270 b is judged to have been cut off. The connection test isperformed in this way.

[0137] The semiconductor integrated circuit device 6 according to thesixth embodiment as described above includes a semiconductor integratedcircuit chip (Chip 250) provided with a plurality of PADs (PADs 260a-260 d), a plurality of LEADs (LEADs 270 a-270 d) disposed around thesemiconductor integrated circuit chip (Chip 250), and two bonding wires(280 a and 280 b) for respectively connecting one LEAD (LEAD 270 b) ofthe plurality of LEADs (LEADs 270 a-270 d) to two PADs (PADs 260 a and260 b) of the plurality of PADs (PADs 260 a-260 d).

[0138] Further, in the semiconductor integrated circuit device 6according to the sixth embodiment, the semiconductor integrated circuitchip (Chip 250) includes PADs (PADs 260 c and 260 d) for measuring acurrent flowing between two PADs (PADs 260 a and 260 b) connected to oneLEAD (LEAD 270 b) by two bonding wires (280 a and 280 b) to therebyeffect a connection test on the two bonding wires.

[0139] According to the sixth embodiment as described above, anadvantageous effect is obtained in that since one LEAD (LEAD 270 b) iswired to the two PADs (PADs 260 a and 260 b), the number of LEADs to beused can be reduced. Further, an advantageous effect is obtained in thatsince the PADs (PADs260 c and 260 d) for measuring the current flowingbetween the two PADs (PADs260 a and 260 b) connected to one LEAD(LEAD270 b) to thereby effect the connection test on the two bondingwires are included in the semiconductor integrated circuit device, aconnection test on whether both the PADs are being connected to itscorresponding LEAD by bonding wires, can be carried out.

[0140] Seventh Embodiment

[0141]FIG. 11 is a plan view showing a semiconductor integrated circuitdevice according to a seventh embodiment of the present invention. InFIG. 11, reference numeral 7 indicates a semiconductor integratedcircuit device, and reference numeral 251 indicates a semiconductorintegrated circuit chip (Chip), respectively. Reference numerals 261a-261 e indicate pads (PADs) of the Chip 251, and reference numerals 271a-271 d indicate leads (LEADs) disposed around the Chip 251,respectively. Reference numerals 281 a and 281 b indicate bonding wiresrespectively. Reference numeral 291 indicates an ammeter with a dc powersupply (unillustrated) provided thereinside. Reference numerals 301a-301 d indicate chip-in wires of the Chip251.

[0142] Electrical connections will next be explained.

[0143] The PAD 261 c of the Chip 251 is connected to its correspondingLEAD 271 b by the bonding wire 281 b. The PAD 261 a and the PAD 261 bare respectively connected to the chip-in wire 301 a and the chip-inwire 301 b, and the PAD 261 b is connected to its corresponding PAD 261c by the chip-in wire 301 b. The PAD 261 a and PAD 261 b are connectedto each other by the bonding wire 281 a. The PAD 261 d and PAD 261 e arerespectively connected to the PAD 261 b and PAD 261 a by the chip-inwire 301 d and chip-in wire 301 c. The ammeter 291 is connected betweenthe PAD 261 d and PAD 261 e.

[0144] While the ammeter 291 is connected between the PAD 261 dconnected to the PAD 261 b by the chip-in wire 301 d and the PAD 261 econnected to the PAD 261 a by the chip-in wire 301 c in thesemiconductor integrated circuit device shown in FIG. 11, it may bedirectly connected between the PAD 261 b and the PAD 261 a.

[0145] The operation of the semiconductor integrated circuit device willnext be described.

[0146] The PAD 261 c of the Chip251 is connected to its correspondingLEAD 271 b by the bonding wire 281 b, the PAD 261 b is connected to itscorresponding PAD 261 c by the chip-in wire 301 b, and the PAD 261 a isconnected to its corresponding PAD 261 b by the bonding wire 281 a.Thus, the transfer of a signal is performed between the PAD 261 a andPAD 261 b, and the LEAD 271 b (when the LEAD 271 b is of a signal LEAD)or the supply of power is performed therebetween (when the LEAD 271 b isof a power LEAD). In FIG. 11, the chip-in wire 301 a and chip-in wire301 b are shown as chip-in wires for a power supply, and the LEAD 271 bis shown as a power LEAD, respectively.

[0147] A connection test executed by the ammeter 291 in the seventhembodiment is based on the following principle.

[0148] Firstly, when the PAD 261 a and PAD 261 b are connected to eachother by the bonding wire 281 a, paths along which currents measured bythe ammeter 291 flow, may include two paths: a first path which extendsfrom the PAD 261 e to the PAD 261 d via the chip-in wire 301 c, the PAD261 a, the bonding wire 281 a, the PAD 261 b, and the chip-in wire 301d, and a second path which extends from the PAD 261 e to the PAD 261 dvia the chip-in wire 301 c, the PAD 261 a, unillustrated other chip-inwires between the PAD 261 a and the PAD 261 b, the PAD261 b, and thechip-in wire 301 d.

[0149] Next, when the PAD 261 a and PAD 261 b are not connected to eachother by the bonding wire 281 a, only the second path referred to aboveis taken as the path along which the current measured by the ammeter 291flows. Thus, as compared with the case where the currents flow in boththe first path and the second path (i.e., where both the PAD 261 a andPAD 261 b are connected to each other by the bonding wire 281 a), theresistance value of the path along which the current flows, increasesand hence the value of the current is reduced.

[0150] Thus, a current value at the time that both the PAD 261 a and PAD261 b are connected to each other by the bonding wire 281 a, is regardedas a normal value. Further, when the current value is relatively lowerthan the normal value, the electrical connection between the PAD 261 aand the PAD 261 b is judged to have been cut off. The connection test isperformed in this way.

[0151] The semiconductor integrated circuit device 7 according to theseventh embodiment as described above includes a semiconductorintegrated circuit chip (Chip 251) provided with a plurality of PADs(PADs 261 a-261 e), a plurality of LEADs (LEADs 271 a-271 d) disposedaround the semiconductor integrated circuit chip (Chip 251), and abonding wire (281 a) for connecting between power supplies (chip-inwires 301 a and 301 b) lying within the semiconductor integrated circuitchip (Chip 251).

[0152] Further, in the semiconductor integrated circuit device 7according to the seventh embodiment, the semiconductor integratedcircuit chip (Chip 251) includes PADs (PADs 261 d and 261 e) formeasuring a current flowing between the power supplies (chip-in wires301 a and 301 d) lying within the semiconductor integrated circuit chip(Chip 251) to thereby effect a connection test on the bonding wire (281a) for connecting between the power supplies.

[0153] According to the seventh embodiment as described above, anadvantageous effect is obtained in that since the bonding wire (bondingwire 281 a) connects between the power supplies (chip-in wires 301 a and301 b) lying within the semiconductor integrated circuit chip (Chip251), power enhancement can be made between the power supplies, and thearea of a power-supply wiring region can be reduced to diminish the areaof the semiconductor integrated circuit chip. Further, an advantageouseffect is obtained in that since the PADs (PADs 261 d and 261 e) formeasuring the current flowing between the power supplies (chip-in wires301 a and 301 d) lying within the semiconductor integrated circuit chip(Chip 251) to thereby effect the connection test on the bonding wire(bonding wire 281 a) for connecting between the power supplies areincluded in the semiconductor integrated circuit chip, a connection teston whether the bonding wire is connecting between the power supplies,can be carried out.

[0154] Eighth Embodiment

[0155]FIG. 12 is a plan view showing a semiconductor integrated circuitdevice according to an eighth embodiment of the present invention. InFIG. 12, reference numeral 8 indicates a semiconductor integratedcircuit device, and reference numeral 15 indicates a bonding pad(bonding PAD), respectively. Reference numeral 252 indicates asemiconductor integrated circuit chip (Chip) disposed on the bonding PAD15. Reference numerals 310 a-310 d, 310 j-310 l, 310 r, and 310 u-310 windicate pads (PADs) of the Chip 252. Reference numerals 320 k, 320 land 320 r indicate leads (LEADs) disposed around an array of the Chip252 disposed on the bonding PAD 15. Reference numerals 330 a and 330 brespectively indicate power leads (VDD), reference numeral 330 a 1indicates an outwardly-extending portion of the VDD 330 a, referencenumerals 330 a 2 and 330 a 3 respectively indicate portions of the VDD330 a, which extend along the periphery of the array of the Chip 252,reference numeral 330 b 1 indicates an outwardly-extending portion ofthe VDD 330 b, and reference numerals 330 b 2 and 330 b 3 respectivelyindicate portions of the VDD 330 b, which extend along the periphery ofthe array of the Chip 252. Reference numerals 340 a and 340 brespectively indicate ground leads (GND), reference numeral 340 a 1indicates an outwardly-extending portion of the GND 340 a, referencenumerals 340 a 2 and 340 a 3 respectively indicate portions of the GND340 a, which extend along the periphery of the array of the Chip 252,reference numeral 340 b 1 indicates an outwardly-extending portion ofthe GND 340 b, and reference numerals 340 b 2 and 340 b 3 respectivelyindicate portions of the GND 340 b, which extend along the periphery ofthe array of the Chip 252. Reference numerals 350 a-350 d, 350 j-350 l,350 r, 350 u-350 w, 351 a and 351 b indicate bonding wires respectively.Reference numerals 360 a and 360 b respectively indicate bonding PADfixing leads (LEADs) for fixing the bonding PAD 15.

[0156] Electrical connections will next be described.

[0157] The PADs 310 a, 310 c, 310 u and 310 w of the Chip 252 arerespectively connected to the VDD 330 b by means of the bonding wires350 a, 350 c, 350 u and 350 w. The PADs 310 b, 310 d and 310 v arerespectively connected to the GND 340 b by means of the bonding wires350 b, 350 d and 350 v. The PAD 310 j is connected to the GND 340 a bythe bonding wire 350 j. The PADs 310 k, 310 l and 310 r are respectivelyconnected to the LEADs 320 k, 320 l and 320 r by means of the bondingwires 350 k, 350 l and 350 r. The VDD 330 a and VDD 330 b are connectedto each other by the bonding wire 351 a. The GND 340 a and GND340 b areconnected to each other by the bonding wire 351 b.

[0158] While both the VDD 330 a and VDD 330 b respectively have theportions extending along the periphery of the Chip 252 and the portionsextending along the bonding PAD fixing LEAD 360 b in the semiconductorintegrated circuit device shown in FIG. 12, either one of the VDD 330 aand VDD 330 b may have only the portions extending along the peripheryof the Chip252. Similarly, while both the GND 340 a and GND 340 brespectively have the portions extending along the periphery of the Chip252 and the portions extending along the bonding PAD fixing LEAD 360 a,either one of the GND 340 a and GND 340 b may have only the portionsextending along the periphery of the Chip 252.

[0159] The operation of the semiconductor integrated circuit device willnext be described.

[0160] Since the PADs 310 k, 310 l and 310 r are respectively connectedto the signal LEADs 320 k, 320 l and 320 r, the transfer of signals isperformed between theses PADs and LEADs respectively. Since the PADs 310a, 310 c, 310 u and 310 w are connected to the VDD 330 b, a sourcevoltage is supplied to these PADs. Since the PADs 310 b, 310 d and 310 vare connected to the GND 340 b, and the PAD 310 j is connected to theGND 340 a, these PADs are respectively supplied with a ground potential.

[0161] As described above, the semiconductor integrated circuit device 8according to the eighth embodiment has a semiconductor integratedcircuit chip (Chip252) provided with a plurality of PADs (PADs 310 a-310d, 310 j-310 l, 310 r and 310 u-310 w), one or a plurality of LEADs(LEADs 320 k, 320 l and 320 r, VDDs 330 a and 330 b, and GNDs 340 a and340 b) disposed around the array of the semiconductor integrated circuitchip (Chip 252), and a plurality of bonding wires (bonding wires 350a-350 d, 350 j-350 l, 350 r and 350 u-350 w). At least one LEAD (VDD 330b, GND 340 b) of the plurality of LEADs are connected to two or morePADs (PADs 310 a, 310 c, 310 u and 310 w) of the plurality of PADs bytheir corresponding bonding wires (bonding wires 310 a, 310 c, 310 u and310 w) of the plurality of bonding wires.

[0162] Further, in the semiconductor integrated circuit device 8according to the eighth embodiment, the LEAD (VDD 330 b, GND 340 b)connected to the two or more PADs includes portions (330 b 2, 330 b 3,340 b 2 and 340 b 3) which extend along the periphery of the array ofthe semiconductor integrated circuit chip (Chip252).

[0163] According to the eighth embodiment as described above, anadvantageous effect is obtained in that since at least one LEAD (VDD 330b, GND 340 b) of the plurality of LEADs is connected to the two or morePADs (PADs 310 a, 310 c, 310 u and 310 w) of the plurality of PADs bytheir corresponding bonding wires (bonding wires 310 a, 310 c, 310 u and310 w) of the plurality of bonding wires, the plurality of PADs lyingwithin the semiconductor integrated circuit chip can be supplied withpower.

[0164] Further, an advantageous effect is obtained in that since theLEAD (VDD 330 b, GND 340 b) connected to the two or more PADs includesthe portions (330 b 2, 330 b 3, 340 b 2 and 340 b 3) which extend alongthe periphery of the array of the semiconductor integrated circuit chip(Chip 252), the power supply and ground can easily be connected to theplurality of PADs even from any orientations of the periphery of thesemiconductor integrated circuit chip.

[0165] Ninth Embodiment

[0166]FIG. 13 is a plan view showing a semiconductor integrated circuitdevice according to a ninth embodiment of the present invention. In FIG.13, reference numeral 9 indicates a semiconductor integrated circuitdevice, and reference numeral 16 indicates a bonding pad (bonding PAD),respectively. Reference numeral 253 indicates a semiconductor integratedcircuit chip A (Chip A) disposed on the bonding PAD16, and referencenumeral 254 indicates a semiconductor integrated circuit chip B (Chip B)disposed on the bonding PAD16, respectively. Reference numerals 311a-311 h, 311 j, 311 m, 311 n, and 311 p indicate pads (PADs) of the ChipA253. Reference numerals indicate 312 h, and 312 i indicate pads (PADs)of the Chip B254. Reference numerals 321 a-321 i indicate leads (LEADs)disposed around arrays of the Chip A253 and Chip B254 disposed on thebonding PAD16. Reference numerals 331 a, 331 b and 331 c respectivelyindicate power LEADs. Reference numerals 352 a-352 h, 352 j, 352 m, 352n, 352 p, 353 h, 353 i, 354 a and 354 b indicate bonding wiresrespectively. Reference numerals 361 a and 361 b respectively indicatebonding PAD fixing leads (LEADs) for fixing the bonding PAD 16.

[0167] Electrical connections will next be described.

[0168] The PADs 311 a, 311 b, 311 d, 311 e, 311 g, 311 j and 311 m ofthe Chip A253 are respectively connected to the LEADs 321 a, 321 b, 321d, 321 e, 321 g, 321 f and 321 c by the bonding wires 352 a, 352 b, 352d, 352 e, 352 g, 352 j and 352 m. The PADs 312 h and 312 i of the ChipB254 are respectively connected to the LEADs 321 h and 321 i by thebonding wires 353 h and 353 i. The PADs 311 c, 311 f and 311 n of theChip A253 are respectively connected to the power LEAD 331 c by thebonding wires 352 c, 352 f and 352 n. The PADs 311 h and 311 p of theChip A253 are respectively connected to the power LEADs 331 a and 331 bby the bonding wires 352 h and 352 p.

[0169] While the power LEAD 331 c has only a portion extending along theperiphery of the Chip A253 in the semiconductor integrated circuitdevice shown in FIG. 13, it may further include two portions whichextend along other LEADs toward the outside of the semiconductorintegrated circuit device from both ends of the power LEAD 331 c. Afurther LEAD including a portion extending along the periphery of theChip A253 is further provided, and the power LEAD 331 c may be used as aLEAD (VDD) for a source voltage. The further LEAD may be used as a LEAD(GND) for ground.

[0170] The operation of the semiconductor integrated circuit device willnext be described.

[0171] Since the PADs 311 a, 311 b, 311 d, 311 e, 311 g, 311 j and 311 mof the Chip A253, and the PADs 312 h and 312 i of the Chip B254 arerespectively connected to the signal LEADs 321 a, 321 b, 321 d, 321 e,321 g, 321 f, 321 c, 321 h and 321 i, the transfer of signals isperformed between these PADs and LEADs respectively. Since the PADs 311c, 311 f and 311 n are connected to the power LEAD 331 c, and the powerLEAD 331 c is connected to the power LEADs 331 a and 331 b eachconnected to an external power supply, these PADs are respectivelysupplied with a source voltage. Since the PADs 311 h and 311 p arerespectively connected to the power LEADs 331 a and 331 b each connectedto the external power supply, these PADs are respectively supplied withthe source voltage.

[0172] As described above, the semiconductor integrated circuit device 9according to the ninth embodiment has semiconductor integrated circuitchips (Chip A253 and Chip B254) provided with a plurality of PADs (PADs311 a-311 h, 311 j, 311 m, 311 n, 311 p, 312 h and 312 i), one or aplurality of LEADs (LEADs 321 a-321 i and 331 a-331 c) disposed aroundthe arrays of the semiconductor integrated circuit chips (Chip A253 andChip B254), and a plurality of bonding wires (352 a-352 h, 352 j, 352 m,352 n, 352 p, 353 h, 353 i, 354 a and 354 b). At least one LEAD (LEAD331c) of the plurality of LEADs is connected to two or more PADs (PADs311c, 311 f and 311 n) of the plurality of PADs by their correspondingbonding wires (352 c, 352 f and 352 n) of the plurality of bondingwires.

[0173] Further, in the semiconductor integrated circuit device 9according to the ninth embodiment, the LEAD (LEAD 331 c) connected tothe two or more PADs includes the portion extending along the peripheryof the array of the semiconductor integrated circuit chip and isconnected to the LEADs (LEADs 331 a and 331 b) different from the LEADconnected to the two or more PADs, by the bonding wires (354 a and 354b).

[0174] According to the ninth embodiment as described above, anadvantageous effect is obtained in that since at least one LEAD (LEAD331 c) of the plurality of LEADs is connected to the two or more PADs(PADs 311 c, 311 f and 311 n) of the plurality of PADs by theircorresponding bonding wires (352 c, 352 f and 352 n) of the plurality ofbonding wires, the plurality of PADs lying within the semiconductorintegrated circuit chip can be supplied with power.

[0175] Further, an advantageous effect is obtained in that since theLEAD (LEAD 331 c) connected to the two or more PADs includes the portionextending along the periphery of the array of the semiconductorintegrated circuit chip and is connected to the LEADs (LEADs 331 a and331 b) different from the LEAD connected to the two or more PADs, by thebonding wires (354 a and 354 b), the plurality of PADs are respectivelysupplied with power from the LEADs directly non-connected to theexternal power supply, and the LEADs which have heretofore been used asthe power LEADs, can be used as signal LEADs.

[0176] Tenth Embodiment

[0177]FIG. 14 is a plan view showing a semiconductor integrated circuitdevice according to a tenth embodiment of the present invention. FIG. 15is a diagrammatic illustration of the semiconductor integrated circuitdevice according to the tenth embodiment. In FIG. 14, reference numeral501 indicates a semiconductor integrated circuit device, and referencenumeral 255 indicates a semiconductor integrated circuit chip (Chip),respectively. Reference numeral 332 indicates a power lead (LEAD)disposed around an array of the Chip 255. Reference numeral 332 aindicates an outwardly-extending portion of the power LEAD 332, andreference numerals 332 b and 332 c respectively indicate portions of thepower LEAD 332, which extend along the periphery of the array of theChip 255. Reference numerals 370 j, 370 k, 370 p and 370 u-370 xindicate pads (PADs) of the Chip 255 respectively. Reference numerals355 u-355 x indicate bonding wires respectively. Reference numerals 302j, 302 k, 302 p and 302 u-302 x indicate chip-in wires of the Chip 255respectively. Reference numeral 292 indicates an ammeter with a dc powersupply (not shown) provided thereinside. Reference numeral 400 indicatesa selector, and reference numeral 410 indicates a register. In FIG. 15,reference numeral 420 a indicates a resistor indicative of a resistancevalue between the PAD 370 u and the PAD 370 v, reference numeral 420 bindicates a resistor indicative of a resistance value between the PAD370 v and the PAD 370 w, and reference numeral 420 c indicates aresistor indicative of a resistance value between the PAD 370 w and thePAD370 u, respectively.

[0178] Electrical connections will next be explained.

[0179] The PADs 370 u, 370 v, 370 w and 370 x are respectively connectedto the power LEAD 332 by the bonding wires 355 u, 355 v, 355 w and 355x. The PADs 370 u, 370 v, 370 w and 370 x are respectively connected tothe selector 400 by the chip-in wires 302 u, 302 v, 302 w and 302 x. ThePADs 370 j and 370 k are connected to the ammeter 292. The PADs 370 jand 370 k are connected to the selector 400 by the chip-in wires 302 jand 302 k. The PAD 370 p is connected to the register 410 by the chip-inwire 302 p.

[0180] In the semiconductor integrated circuit device shown in FIG. 14,another LEAD is provided in addition to the power LEAD 332. The powerLEAD 332 may be used as a LEAD (VDD) for a source voltage, and anotherLEAD may be used as a LEAD (GND) for ground.

[0181] The operation of the semiconductor integrated circuit device willnext be described.

[0182] Since the PADs 370 u-370 x of the Chip 255 are connected to thepower LEAD 322, these PADs are respectively supplied with the sourcevoltage. Since the PAD 370 p is connected to the register 410, selectdata inputted from the PAD 370 p is inputted to the register 410 whereit is stored. Since the PADs 370 j and 370 k connected with the ammeter292 are respectively connected to the selector 400 by the chip-in wire302 j and the chip-in wire 302 k, a current that flows between the twoPADs of the PADs 370 u-370 x, which are selected by the selector 400based on the select data stored in the register 410, is measured by theammeter 292.

[0183] A connection test according to the tenth embodiment is carriedout in the following manner.

[0184] A description will be made of a case in which a connection testamong three PADs of the PADs 370 u, 370 v and 370 w is performed asshown in FIG. 15. The selector 400 selects, for example, the PAD 370 uand PAD 370 v, based on the select data stored in the register 410, andthereby connects the chip-in wire 302 u connected with the PAD 370 u tothe chip-in wire 302 k and connects the chip-in wire 302 v connectedwith the PAD 370 v to the chip-in wire 302 j. Consequently, the ammeter292 is connected to the PAD 370 u and PAD 370 v to thereby measure acurrent value corresponding to a resistance value (corresponding to thevalue represented by the resistor 420 a) between the PAD 370 u and PAD370 v. Thus, a current value at the time that the PAD 370 u and PAD 370v are respectively connected to the power LEAD 332 by the bonding wire355 u and the bonding wire 355 v, is regarded as a normal value.Further, when the current value is relatively lower than the normalvalue, the electrical connection between the PAD 370 u and PAD 370 v isjudged to have been cut off. The connection test is performed in thisway. A connection test is performed similarly even when a combination ofother PADs is selected by the selector 400.

[0185] The semiconductor integrated circuit device 501 according to thetenth embodiment as described above includes a semiconductor integratedcircuit chip (Chip 255) provided with a plurality of PADs (PADs 370 j,370 k, 370 p and 370 u-370 x), one or plural LEADs (power LEAD 332)disposed around an array of the semiconductor integrated circuit chip(Chip 255), and a plurality of bonding wires (bonding wires 355 u-355x). At least one LEAD (power LEAD 332) of the plurality of LEADs isconnected to two or more PADs (PADs 370 u, 370 v, 370 w and 370 x) ofthe plurality of PADs by the corresponding bonding wires (bonding wires355 u-355 x) of the plurality of bonding wires.

[0186] In the semiconductor integrated circuit device 501 according tothe tenth embodiment as well, the LEAD (power LEAD 332) connected to twoor more PADs includes portions (332 b and 332 c) which extend along thearray of the semiconductor integrated circuit chip (Chip 255).

[0187] Further, in the semiconductor integrated circuit device 501according to the tenth embodiment, the semiconductor integrated circuitchip (Chip 255) includes PADs (PADs 370 j and 370 k) for measuringcurrents flowing between two or more PADs (PADs 370 u-370 x) connectedto one LEAD and thereby effecting a connection test on the bonding wires(355 u-355 x) for connecting between the respective PADs.

[0188] Furthermore, in the semiconductor integrated circuit device 501according to the tenth embodiment, the semiconductor integrated circuitchip (Chip 255) further includes a selector (400) for selecting two PADsto be measured.

[0189] According to the tenth embodiment as described above, anadvantageous effect is obtained in that since at least one LEAD (powerLEAD 332) of the plurality of LEADs is connected to the two or more PADs(PADs 370 u, 370 v, 370 w and 370 x) of the plurality of PADs by itscorresponding bonding wires (bonding wires 355 u-355 x) of the pluralityof bonding wires, the plurality of PADs lying within the semiconductorintegrated circuit chip can be supplied with power.

[0190] An advantageous effect is also obtained in that since the LEAD(power LEAD 332) connected to the two or more PADs includes the portions(332 b and 332 c) extending along the periphery of the array of thesemiconductor integrated circuit chip (Chip 255), the power supply andground can easily be connected to the plurality of PADs even from anyorientations of the periphery of the semiconductor integrated circuitchip.

[0191] Further, an advantageous effect is obtained in that since thesemiconductor integrated circuit chip (Chip 255) includes the PADs (PADs370 j and 370 k) for measuring currents flowing between the two or morerespective PADs (PADs 370 u-370 x) connected to one LEAD and therebyeffecting the connection test on the bonding wires (355 u-355 x) forconnecting between the respective PADs, a connection test on whether therespective PADs are connected to the LEAD by their corresponding bondingwires, can be done.

[0192] Furthermore, an advantageous effect can be obtained in that sincethe semiconductor integrated circuit chip (Chip 255) further includesthe selector (400) for selecting the two PADs to be measured, the PADsfor carrying out the connection test are selected to allow a currentmeasurement.

[0193] Eleventh Embodiment

[0194]FIG. 16 is a plan view showing a semiconductor integrated circuitdevice according to the eleventh embodiment of the present invention. InFIG. 16, reference numeral 502 indicates a semiconductor integratedcircuit device, and reference numeral 256 indicates a semiconductorintegrated circuit chip (Chip), respectively. Reference numerals 430a-430 c indicate pads (PADs) of the Chip256, and reference numerals 480a, 480 b and 481 a-481 e indicate chip-in wires, respectively. Referencenumerals 440 a-440 d indicate diodes which constitute temperaturesensors. Reference numeral 401 indicates a selector, and referencenumeral 450 indicates a voltmeter, respectively. Reference numeral 460indicates ground (GND).

[0195] Electrical connections will next be explained.

[0196] The diodes 440 a-440 d are connected in series. The anode of thediode 440 a, the anode of the diode 440 b, the anode of the diode 440 c,the anode of the diode 440 d, and the cathode of the diode 440 d arerespectively connected to the selector 401 by the chip-in wires 481 a,481 b, 481 c, 481 d and 481 e. The anode of the diode 440 a is connectedeven to the PAD 430 c, and the cathode of the diode 440 d is connectedto the ground (GND) 460. An external power (not shown) for causing acurrent to flow through the diodes 440 a-440 d connected in series isconnected to the PAD 430 c. As shown in FIG. 16, the series-connecteddiodes 440 a-440 d are linearly disposed along one direction on theplane of the Chip256. The selector 401 is connected to the PAD 430 a andPAD 430 b by the chip-in wire 480 a and the chip-in wire 480 b, and thevoltmeter 450 is connected between the PAD 430 a and the PAD 430 b. Aregister (not shown) is connected to the selector 401 and PADs (notshown) are connected to the register.

[0197] The operation of the semiconductor integrated circuit device willnext be described.

[0198] In order to select any one of the diodes 440 a-440 d, based onselect data stored in the register (not shown), the selector 401connects a pair of the chip-in wires of the chip-in wires 481 a-481 e tothe chip-in wire 480 a and the chip-in wire 480 b connected to the PAD430 a and PAD 430 b. The voltmeter 450 measures a voltage between theanode and cathode of the diode connected with the pair of chip-in wiresconnected to the PAD 430 a and PAD 430 b via the selector 401. Thetemperature of the Chip 256 placed in the position where the diodeselected by the selector 401 is disposed, can be recognized based on thevoltage measured by the voltmeter 450. The selector 401 selects thecontinuously-connected two or more diodes of the diodes 440 a-440 d,based on the select data stored in the register (not shown). A wholevoltage of the continuously-connected two or more diodes may be measuredby the voltmeter 450.

[0199] As described above, the semiconductor integrated circuit device502 according to the eleventh embodiment has a semiconductor integratedcircuit chip (Chip 256) provided with a plurality of PADs (PADs 430a-430 c), and a plurality of temperature sensors (440 a-440 d) formeasuring a temperature distribution within the semiconductor integratedcircuit chip (Chip 256).

[0200] Further, in the semiconductor integrated circuit device 502according to the eleventh embodiment, the plurality of temperaturesensors (440 a-440 d) are disposed within a semiconductor integratedcircuit chip as an array comprising a plurality of temperature sensorsconnected in series.

[0201] Furthermore, in the semiconductor integrated circuit device 502according to the eleventh embodiment, the semiconductor integratedcircuit chip (Chip 256) further includes a selector (401) for selectingthe temperature sensors (440 a-440 d).

[0202] According to the eleventh embodiment as described above, anadvantageous effect is obtained in that since the plurality oftemperature sensors (440 a-440 d) for measuring a temperaturedistribution within the semiconductor integrated circuit chip (Chip 256)are provided, the temperature distribution within the semiconductorintegrated circuit chip (Chip 256) is recognized and thereby estimated,thereby making it possible to reduce the size of the semiconductorintegrated circuit chip.

[0203] An advantageous effect is obtained in that since the plurality oftemperature sensors (440 a-440 d) are disposed within the semiconductorintegrated circuit chip as the array comprising the plurality oftemperature sensors connected in series, a temperature distribution at aposition along the array comprised of the temperature sensors can berecognized.

[0204] An advantageous effect is obtained in that since thesemiconductor integrated circuit chip (Chip 256) further includes theselector (401) for selecting the temperature sensors (440 a-440 d),temperatures at positions where the respective temperature sensors aredisposed, can be measured.

[0205] Twelfth Embodiment

[0206]FIG. 17 is a plan view showing a semiconductor integrated circuitdevice according to a twelfth embodiment of the present invention. InFIG. 17, reference numeral 503 indicates a semiconductor integratedcircuit device, and reference numeral 257 indicates a semiconductorintegrated circuit chip (Chip), respectively. Reference numerals 431a-431 c indicate pads (PADs) of the Chip257. Reference numerals 482 a,482 b, 483 a-481 e, 484 a-484 c, 485 a-485 c and 486 indicate chip-inwires respectively. Reference numerals 441 a-441 d, 442 a-442 d and 443a-443 d indicate diodes which constitute temperature sensors. Referencenumeral 402 indicates a selector, and reference numeral 451 indicates avoltmeter, respectively. Reference numerals 461 a-461 c indicate grounds(GNDs). Reference numeral 470 indicates a switch.

[0207] Electrical connections will next be described.

[0208] The diodes 441 a-441 d are connected in series. The anode of thediode 441 a, the anode of the diode 441 b, the anode of the diode 441 c,the anode of the diode 441 d and the cathode of the diode 441 d arerespectively connected to the selector 402 by the chip-in wires 483 a,483 b, 483 c, 483 d and 483 e. The diodes 442 a-442 d and the diodes 443a-443 d are connected in series and connected to the selector 402 in amanner similar to the diodes 441 a-441 d. The anode of the diode 441 ais connected even to the switch 470 by the chip-in wire 484 a, and thecathode of the diode 441 d is connected even to the ground (GND) 461 aby the chip-in wire 485 a. The anode of the diode 442 a is connectedeven to the switch 470 by the chip-in wire 484 b, and the cathode of thediode 442 d is connected even to the ground (GND) 461 b by the chip-inwire 485 b. The anode of the diode 443 a is connected even to the switch470 by the chip-in wire 484 c, and the cathode of the diode 443 d isconnected even to the ground (GND) 461 c by the chip-in wire 485 c. Asshown in FIG. 17, the series-connected diodes 441 a-441 d, theseries-connected diodes 442 a-442 d and the series-connected diodes 443a-443 d respectively constitute arrays comprising a plurality oftemperature sensors linearly disposed along one direction on the planeof the Chip257. The arrays comprising these plural temperature sensorsare parallel-connected to one another and disposed along a directionorthogonal to the one direction on the plane of the Chip 257. Theselector 402 is connected to the PAD431 a and PAD431 b by the chip-inwire 482 a and the chip-in wire 482 b, and the voltmeter 451 isconnected between the PAD431 a and the PAD431 b. A register (not shown)is connected to the selector 402, and PADs (not shown) are connected tothe register. The switch 470 is connected to the PAD431 c by the chip-inwire 486. An external power supply (not shown) for allowing currents toflow through the diodes 441 a through 441 d, 442 a through 442 d and 443a through 443 d connected in series is connected to the PAD431 c.

[0209] The operation of the semiconductor integrated circuit device willnext be described.

[0210] In order to select any one of the arrays 441 a-441 d, 442 a-442 dand 443 a-443 d comprising the series-connected diodes, based on selectdata stored in the register (not shown), the switch 470 connects any oneof the chip-in wires 484 a through 484 c to the PAD 431 c. In order toselect the diode of any one of the arrays of the series-connecteddiodes, which has been selected by the switch 470, based on the selectdata stored in the register (not shown), the selector 402 connects apair of chip-in wires of the chip-in wires 483 a through 483 e to thechip-in wire 482 a and chip-in wire 482 b connected to the PAD 431 a andPAD 431 b. The voltmeter 451 measures a voltage between the anode andcathode of the diode connected with the pair of chip-in wires connectedto the PAD 431 a and PAD431 b via the selector 402. The temperature ofthe Chip257 placed in the position where the diode selected by theselector 402 is disposed, can be recognized based on the voltagemeasured by the voltmeter 451. The selector 402 selects thecontinuously-connected two or more diodes of the array of theseries-connected diodes selected by the switch 470, based on the selectdata stored in the register (not shown). Then, a whole voltage acrossthe continuously-connected two or more diodes may also be measured bythe voltmeter 451.

[0211] As described above, the semiconductor integrated circuit device503 according to the twelfth embodiment has a semiconductor integratedcircuit chip (Chip 257) provided with a plurality of PADs (PADs 431a-431 c), and a plurality of temperature sensors (441 a-441 d, 442 a-442d and 443 a-443 d) for measuring a temperature distribution within thesemiconductor integrated circuit chip (Chip 257).

[0212] Further, in the semiconductor integrated circuit device 503according to the twelfth embodiment, the plurality of temperaturesensors (441 a-441 d, 442 a-442 d and 443 a-443 d) are disposed within asemiconductor integrated circuit chip as plural arrays (441 a-441 d, 442a-442 d and 443 a-443 d) in which arrays comprising a plurality oftemperature sensors connected in series are parallel-connected to oneanother.

[0213] Furthermore, in the semiconductor integrated circuit device 503according to the twelfth embodiment, the semiconductor integratedcircuit chip (Chip 257) further includes a switch (470) for selectingarrays comprising temperature sensors and a selector (402) for selectingthe temperature sensors of the respective arrays.

[0214] According to the twelfth embodiment as described above, anadvantageous effect is obtained in that since the plurality oftemperature sensors (441 a-441 d, 442 a-442 d and 443 a-443 d) formeasuring a temperature distribution lying within the semiconductorintegrated circuit chip (Chip 257) are provided, the temperaturedistribution within the semiconductor integrated circuit chip (Chip 257)is recognized and thereby estimated, thereby making it possible toreduce the size of the semiconductor integrated circuit chip.

[0215] An advantageous effect is obtained in that since the plurality oftemperature sensors (441 a-441 d, 442 a-442 d and 443 a-443 d) aredisposed within the semiconductor integrated circuit chip as the pluralarrays (441 a-441 d, 442 a-442 d and 443 a-443 d) in which the arrayscomprising the plurality of temperature sensors connected in series areparallel-connected to one another, temperature distributions atpositions along the individuals of the arrays comprising the temperaturesensors can be recognized.

[0216] An advantageous effect is obtained in that since thesemiconductor integrated circuit chip (Chip257) further includes aswitch (470) for selecting the arrays comprised of the temperaturesensors, and the selector (402) for selecting the temperature sensors ofthe respective arrays, temperatures at positions where the respectivetemperature sensors are disposed, can be measured.

What is claimed is:
 1. A semiconductor integrated circuit device,comprising: at least two semiconductor integrated circuit chipsrespectively provided with a plurality of PADs; a plurality of LEADsdisposed around arrays of said semiconductor integrated circuit chips;and a plurality of bonding wires; wherein said plurality of bondingwires are connected so as not to straddle one semiconductor integratedcircuit chip and allow wiring between said PADs of the other integratedcircuit chip and said LEADs.
 2. The semiconductor integrated circuitdevice according to claim 1, wherein the one semiconductor integratedcircuit chip includes I/F functions between the other semiconductorintegrated circuit chip and LEADs.
 3. The semiconductor integratedcircuit device according to claim 1, further including a thirdsemiconductor integrated circuit chip provided with a plurality of PADs,and wherein said third semiconductor integrated circuit chip includesI/F functions between the other semiconductor integrated circuit chipand the one semiconductor integrated circuit chip, and I/F functionsbetween the one semiconductor integrated circuit chip and LEADs.
 4. Thesemiconductor integrated circuit device according to claim 1, furtherincluding, a third semiconductor integrated circuit chip disposed underthe one semiconductor integrated circuit chip; and a height adjustingsemiconductor integrated circuit chip provided with a plurality of PADs,which is disposed on said third semiconductor integrated circuit chip,adjacent to the one semiconductor integrated circuit chip, and whereinsaid height adjusting semiconductor integrated circuit chip has I/Ffunctions between the other semiconductor integrated circuit chip andLEADs, and the plurality of PADs of said height adjusting semiconductorintegrated circuit chip are disposed on the same plane as the pluralityof PADs of the other semiconductor integrated circuit chip.
 5. Thesemiconductor integrated circuit device according to claim 1, furtherincluding an I/F semiconductor integrated circuit chip provided with aplurality of PADs, which is disposed under the one semiconductorintegrated circuit chip, and wherein said I/F semiconductor integratedcircuit chip has I/F functions between the other semiconductorintegrated circuit chip and LEADs.
 6. The semiconductor integratedcircuit device according to claim 1, including LEADs which extend underthe one semiconductor integrated circuit chip and reach theircorresponding positions adjacent to the other semiconductor integratedcircuit chip.
 7. A semiconductor integrated circuit device, comprising:a semiconductor integrated circuit chip provided with a plurality ofPADs; a plurality of LEADs disposed around said semiconductor integratedcircuit chip; and two bonding wires for connecting one LEAD of saidplurality of LEADs to the two PADs of said plurality of PADs.
 8. Thesemiconductor integrated circuit device according to claim 7, whereinsaid semiconductor integrated circuit chip includes PADs for measuring acurrent flowing between two PADs connected to one LEAD by two bondingwires to thereby effect a connection test on the two bonding wires.
 9. Asemiconductor integrated circuit device, comprising: a semiconductorintegrated circuit chip provided with a plurality of PADs; a pluralityof LEADs disposed around said semiconductor integrated circuit chip; anda bonding wire for connecting between power supplies lying within saidsemiconductor integrated circuit chip.
 10. A semiconductor integratedcircuit device, comprising: a semiconductor integrated circuit chipprovided with a plurality of PADs; one or a plurality of LEADs disposedaround an array of said semiconductor integrated circuit chip; and aplurality of bonding wires; wherein at least one LEAD of said pluralityof LEADs is connected to two or more PADs of the plurality of PADs bythe corresponding bonding wires of said plurality of bonding wires. 11.The semiconductor integrated circuit device according to claim 10,wherein a LEAD connected to two or more PADs includes portions extendingalong the periphery of the array of said semiconductor integratedcircuit chip.
 12. The semiconductor integrated circuit device accordingto claim 10, wherein a LEAD connected to two or more PADs includesportions extending along the periphery of the array of saidsemiconductor integrated circuit chip and is connected to LEADsdifferent from the LEAD connected to the two or more PADs by bondingwires.
 13. The semiconductor integrated circuit device according toclaim 10, wherein a LEAD connected to two or more PADs includes portionsextending along the periphery of the array of said semiconductorintegrated circuit chip.
 14. A semiconductor integrated circuit device,comprising: a semiconductor integrated circuit chip provided with aplurality of PADs; and a plurality of temperature sensors for measuringa temperature distribution within said semiconductor integrated circuitchip.
 15. The semiconductor integrated circuit device according to claim14, wherein said plurality of temperature sensors are disposed withinsaid semiconductor integrated circuit chip as plural arrays in which thearrays comprising the plurality of temperature sensors connected inseries are parallel-connected to one another.
 16. The semiconductorintegrated circuit device according to claim 15, wherein saidsemiconductor integrated circuit chip further includes, a switch forselecting the arrays comprising the temperature sensors, and a selectorfor selecting the temperature sensors of the respective arrays.